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fn7908 rev 3.00 page 1 of 17 november 30, 2016 fn7908 rev 3.00 november 30, 2016 ISL78322 dual 2a/1.7a, 2.25mhz high-effici ency, synchronous buck regulat or datasheet the ISL78322 is a high-efficiency, dual synchronous step-down dc/dc regulator that can deliver up to 2a/1.7a continuous output current per channel. the channels are 180 out-of- phase for input rms current an d emi reduction. the supply voltage range of 2.8v to 5.5v a llows for the use of a single li+ cell, three nimh cells or a regulated 5v input. the current mode control architecture enables very low duty cycle operation at high frequency with fast transient response and excellent loop stability. the ISL78322 operates at 2.25mhz switching frequency, which allows for the use of small, low cost inductors and capacitors. each channel is optimized for generating an output voltage as low as 0.6v. the ISL78322 has a forced pwm mode that reduces noise and rf interference. the ISL78322 offers a 1ms power- good (pg) signal to monitor both outputs at power-up. when shut down, ISL78322 discharges the output capacitors. other features include internal digital soft-start, enable for power sequence, overcurrent protection, and thermal shutdown. the ISL78322 is offered in a 4mmx3mm, 12 lead dfn package with 1mm maximum height. the complete converter occupies less than 1.8cm 2 area. the ISL78322 is qualified to aec-q100 and specified for operation across the -40c to +105c (grade 2) ambient temperature range. features ? dual 2a/1.7a high-efficiency, synchronous buck regulator with up to 97% efficiency ? 2.8v to 5.5v input supply range ?180 out-of-phase outputs reduce ripple current and emi ? start-up with prebiased output prevents negative current flow in output stage ? external synchronization up to 8mhz ? negative current detection and protection ? 100% maximum duty cycle for lowest dropout ? internal current mode compensation ? peak current limiting, hiccup mo de short-circuit protection, and over-temperature protection ? pb-free (rohs compliant) ? aec-q100 qualified component applications ? dc/dc pol modules ? c/p, fpga, and dsp power ? automotive embedded processor power supply systems related literature ? for a full list of related documents, visit our website - ISL78322 product page 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 e f f i c i e n c y ( % ) output load (a) 3.3v out2 pwm 2.5v out1 pwm 2.25mhz 5v in at +25c figure 1. characteristic curve
ISL78322 fn7908 rev 3.00 page 2 of 17 november 30, 2016 in table 1 , the minimum output capacitor value is given for different output voltages to make sure the whole converter system is stable. output capacita nce should increase to support faster load transient requirement. typical applications figure 2. typical application diagram - dual independent outputs l 1 1.2h lx1 pgnd fb1 vin en2 pg sync input 2.8v to 5.5v output1 2.5v/2a c 1 2 x 10f ISL78322 c 2 r 2 316k r 3 100k 22f c 3 10pf l 2 1.2h fb2 output2 1.8v/1.7a c 4 r 5 200k r 6 100k 22f c 5 10pf lx2 pgnd en1 ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # ISL78322arz beka -40 to +105 12 ld 4x3 dfn l12.4x3 notes: 1. add ?-t? suffix for 6k unit or ?-t7a? suffix for 250 unit tape and reel options. refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), see device information page for ISL78322 . for more information on msl, see techbrief tb363 . table 1. component value selection v out 0.8v 1.2v 1.5v 1.8v 2.5v 3.3v c 1 2x10f 2x10f 2x10f 2x10f 2x10f 2x10f c 2 (or c 4 ) 22f 22f 22f 22f 22f 22f c 3 (or c 5 ) 10pf 10pf 10pf 10pf 10pf 10pf l 1 (or l 2 ) 1.0~2.2h 1.0~2.2h 1.0~2.2h 1.5~3.3h 1.5~3.3h 1.5~4.7h r 2 (or r 5 ) 33k 100k 150k 200k 316k 450k r 3 (or r 6 ) 100k 100k 100k 100k 100k 100k
ISL78322 fn7908 rev 3.00 page 3 of 17 november 30, 2016 block diagram figure 3. block diagram lx1 + + csa1 + ocp 1.25v + + + slope comp soft start soft- start 0.6v eamp comp pwm logic controller protection driver fb1 + 0.546v pg sync shutdown pgnd oscillator bandgap scp + 0.2v en1 shutdown 1ms delay 27pf 250k 3pf 1.6k lx2 + + csa2 + ocp 1.1v + + + slope comp soft start soft- start eamp comp pwm logic controller protection driver fb2 + shutdown pgnd zero - cross sensing bandgap scp + 0.2v en2 shutdown 3pf 1.6k thermal shut down shutdown 1m vin 0.546v 0.6v vcc 27pf 250k vcc vin2 vin1 negative current limit zero - cross sensing negative current limit
ISL78322 fn7908 rev 3.00 page 4 of 17 november 30, 2016 pin configuration ISL78322 (12 ld dfn) top view fb1 en1 pg vin1 lx1 fb2 en2 sync vin2 lx2 pgnd1 2 3 4 1 5 11 10 9 12 8 6 7 pgnd2 pad pin description pin number symbol description 1 fb1 the feedback network of the channel 1 regulator. fb1 is the negative input to the transconductance error amplifier. the out put voltage is set by an external resistor divider connected to fb1. with a properly selected divider, the output voltage can be se t to any voltage between the power rail (reduced by converter losses) an d the 0.6v reference. there is an internal compensation to meet a typical application. in addition, the regulator power-good and undervoltage protection circuitry use fb1 to monitor the channel 1 regulator output voltage. 2 en1 regulator channel 1 enable pin. enable the output, v out1 , when driven to high. shutdown the v out1 and discharge output capacitor when driven to low. do not leave this pin floating. 3 pg 1ms timer output. at power-up or en_ hi, this output is a 1ms delayed power-good signal for both the v out1 and v out2 voltages. there is an internal 1m pull-up resistor. 4 vin1 input supply voltage for channel 1. connect 10f ceramic capacitor to pgnd1. 5 lx1 switching node connection for channel 1. connect to one terminal of inductor for v out1 . 6 pgnd1 negative supply for power stage 1. 7 pgnd2 negative supply for power stage 2 and system ground. 8 lx2 switching node connection for channel 2. connect to one terminal of inductor for v out2 . 9 vin2 input supply voltage for channel 2 and to provide logic bias. make sure that vin2 is vin1. connect 10f ceramic capacitor to pgnd2. 10 sync connect to logic low or ground for forced pwm mode. connec t to an external function generator for synchronization. negati ve edge trigger. do not leave this pin floating. 11 en2 regulator channel 2 enable pin. enable the output, v out2 , when driven to high. shutdown the v out2 and discharge output capacitor when driven to low. do not leave this pin floating. 12 fb2 the feedback network of the channel 2 regulator. fb2 is the negative input to the transconductance error amplifier. the ou tput voltage is set by an external resistor divider connected to fb2. with a properly selected divider, the output voltage can be se t to any voltage between the power rail (reduced by converter losses) an d the 0.6v reference. there is an internal compensation to meet a typical application. in addition, the regulator power-good and undervoltage protection circuitry use fb2 to monitor the channel 2 regulator output voltage. -exposed pad the exposed pad must be connected to the pgnd1 and pgnd2 pins for proper electrical perfor mance. add as many vias as possible for optimal thermal performance.
ISL78322 fn7908 rev 3.00 page 5 of 17 november 30, 2016 absolute maximum ratings (reference to gnd) thermal information supply voltage (vin) . . . . . . . . . . . . . . . . . . . . -0.3v to 6v (dc) or 7v (20ms) en1, en2, pg, sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to v in + 0.3v lx1, lx2. . . . . . . . . . . . . . . . . . . . . . . -1.5v (100ns)/-0.3v (dc) to 6.5v (dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or 7v (20ms) fb1, fb2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . . 3kv machine model(tested per jesd22-c101e) . . . . . . . . . . . . . . . . . . 250v charged device model (tested per aec-q100-11) . . . . . . . . . . . . . . . 2kv latch-up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 4x3 dfn package ( notes 4 , 5 ) . . . . . . . . 41 3 junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions v in supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8v to 5.5v load current range channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 2a load current range channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 1.7a ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high-effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. ? jc , ?case temperature? location is at the center of the exposed metal pad on the package underside. electrical specifications unless otherwise noted, all parameter limits are established over the recommended operating conditions: t a = -40c to +105c, v in = 2.8v to 5.5v, en1 = en2 = v in , sync = 0v, l = 1.2h, c 1 = 2 x 10f, c 2 = c 4 = 22f, i out1 = 0a to 2a, i out2 = 0a to 1.7a. (typical values are at t a = +25c, v in = 3.6v). boldface limits apply across the operating temperature range, -40c to +105c. parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit input supply v in undervoltage lock-out threshold v uvlo rising 2.5 2.8 v falling 2.0 2.4 v quiescent supply current i vin sync = gnd, en1 = en2 = v in , f sw = 2.25mhz, no load at the output 0.86 1.00 ma shutdown supply current i sd v in = 5.5v, en1 = en2 = gnd 6.5 12.0 a output regulation fb1, fb2 regulation voltage v fb_ 0.590 0.600 0.610 v fb1, fb2 bias current i fb_ v fb = 0.55v 0.1 a output voltage accuracy sync = v in , io = 0a to 2a 1.5 % sync = gnd, io = 0a to 2a 1 % line regulation v in = v o + 0.5v to 5.5v (minimal 2.8v) 0.2 %/v soft-start ramp time cycle 1.3 ms overcurrent protection dynamic current limit on-time t ocon 17 clock pulses dynamic current limit off-time t ocoff 4 ss cycle peak overcurrent limit i pk1 2.7 3.2 3.6 a i pk2 2.3 2.8 3.2 a negative current limit i valley1 -2.2 -1.6 -1.0 a i valley2 -2.2 -1.6 -1.0 a
ISL78322 fn7908 rev 3.00 page 6 of 17 november 30, 2016 lx1, lx2 p-channel mosfet on-resistance v in = 5.5v, i o = 200ma channel 1 90 115 m v in = 5.5v, i o = 200ma channel 2 100 125 m n-channel mosfet on-resistance v in = 5.5v, i o = 200ma channel 1 80 103 m v in = 5.5v, i o = 200ma channel 2 90 112 m lx_ maximum duty cycle 100 ? pwm switching frequency f sw 1.80 2.25 2.70 mhz synchronization range ( note 7 ) 5.4 8.0 mhz channel 1 to channel 2 phase shift rising edge to rising edge timing 180 lx minimum on time sync = high (forced pwm mode) 65 ns soft discharge resistance r dis_ en = low 80 100 130 pg output low voltage sinking 1ma, vfb = 0.5v 0.4 v pg pin leakage current pg = v in = 3.6v 0.01 0.10 a pg pull-up resistor 1m internal pgood low rising threshold percentage of nominal regulation voltage 85 91 97 % internal pgood low falling threshold percentage of nominal regulation voltage 78 85 92 % delay time (rising edge) 0.76 ms internal pgood delay time (falling edge) 2 4 s en1, en2, sync logic input low 0.4 v logic input high 1.4 v enable logic input leakage current i en_ 0.1 1 a thermal shutdown 150 c thermal shutdown hysteresis 25 c notes: 6. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. 7. the operational frequency per switching chan nel will be half of the sync frequency. electrical specifications unless otherwise noted, all parameter limits are established over the recommended operating conditions: t a = -40c to +105c, v in = 2.8v to 5.5v, en1 = en2 = v in , sync = 0v, l = 1.2h, c 1 = 2 x 10f, c 2 = c 4 = 22f, i out1 = 0a to 2a, i out2 = 0a to 1.7a. (typical values are at t a = +25c, v in = 3.6v). boldface limits apply across the operating temperature range, -40c to +105c. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit
ISL78322 fn7908 rev 3.00 page 7 of 17 november 30, 2016 typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 2.8v to 5.5v, en = v in , l 1 = l 2 = 1.2h, c 1 = 10f, c 2 = c 4 = 22f, i out1 = 0a to 2a, i out2 = 0a to 1.7a. figure 4. efficiency vs load, 2.25mhz, 3.3v in pwm figure 5. efficiency vs load, 2.25mhz, 5v in pwm figure 6. power dissipation vs load, 2.25mhz, 1.8v, channel 2 figure 7. v out regulation vs load, 2.25mhz, 1.2v, channel 1 figure 8. v out regulation vs load, 2.25mhz, 1.5v channel 2 figure 9. v out regulation vs load, 2.25mhz, 2.5v channel 1 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 e f f i c i e n c y ( % ) output load (a) 2.5v out1 1.2v out1 1.5v out2 1.8v out2 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 e f f i c i e n c y ( % ) output load (a) 1.2v out1 1.5v out1 3.3v out2 2.5v out1 1.8v out2 0.00 0.15 0.30 0.45 0.60 0.75 0.90 0.00.20.40.60.81.01.21.41.61.82.0 p o w e r d i s s i p a t i o n ( w ) output load (a) 5 v in pwm 3.3v in pwm 1.17 1.18 1.19 1.20 1.21 1.22 1.23 0.00.20.40.60.81.01.21.41.61.82.0 o u t p u t v o l t a g e ( v ) output load (a) 5v in pwm 3.3v v in pwm 1.48 1.49 1.50 1.51 1.52 1.53 1.54 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 o u t p u t v o l t a g e ( v ) output load (a) 3.3v v in pwm 5v in pwm 2.47 2.48 2.49 2.50 2.51 2.52 2.53 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 o u t p u t v o l t a g e ( v ) output load (a) 3.3v v in pwm 5v in pwm
ISL78322 fn7908 rev 3.00 page 8 of 17 november 30, 2016 figure 10. v out regulation vs load, 2.25mhz, 1.8v, channel 2 figure 11. output voltage regulation vs v in 2.5v channel 1 figure 12. output voltage regulation vs v in 1.8v channel 2 figure 13. steady state operation at no load channel 1 (pwm) figure 14. steady state operation at no load channel 2 (pwm) typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 2.8v to 5.5v, en = v in , l 1 = l 2 = 1.2h, c 1 = 10f, c 2 = c 4 = 22f, i out1 = 0a to 2a, i out2 = 0a to 1.7a. (continued) 1.77 1.78 1.79 1.80 1.81 1.82 1.83 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 o u t p u t v o l t a g e ( v ) output load (a) 5v in pwm 3.3v v in pwm 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5 o u t p u t v o l t a g e ( v ) input voltage (v) 1a load 2a load 0a load pwm 1.77 1.78 1.79 1.80 1.81 1.82 1.83 2.52.83.13.43.74.04.34.64.95.25.5 o u t p u t v o l t a g e ( v ) input voltage (v) 0.8a load 1.7a load 0a load pwm lx1 2v/div il1 0.2a/div v out1 ripple 20mv/div tb = 200ns/div lx2 2v/div il2 0.2a/div v out2 ripple 20mv/div tb = 200ns/div
ISL78322 fn7908 rev 3.00 page 9 of 17 november 30, 2016 figure 15. steady state operation at full load channel 1 f igure 16. steady state operatio n with full load channel 2 figure 17. load transient channel 1 (pwm) figure 18. load transient channel 2 (pwm) figure 19. soft-start with no load channel 1 (pwm) figure 20. soft-start with no load channel 2 (pwm) typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 2.8v to 5.5v, en = v in , l 1 = l 2 = 1.2h, c 1 = 10f, c 2 = c 4 = 22f, i out1 = 0a to 2a, i out2 = 0a to 1.7a. (continued) lx1 2v/div il1 1a/div v out1 ripple 20mv/div tb = 200ns/div lx2 2v/div il2 1a/div v out2 ripple 20mv/div tb = 200ns/div il1 1a/div v out1 ripple 50mv/div pg 5v/div tb = 200s/div pg 5v/div il2 1a/div v out2 ripple 50mv/div tb = 200s/div en1 2v/div il1 0.5a/div v out1 1v/div pg 5v/div tb = 500s/div en2 2v/div il2 0.5a/div v out2 1v/div pg 5v/div tb = 500s/div
ISL78322 fn7908 rev 3.00 page 10 of 17 november 30, 2016 figure 21. soft-start at full load channel 1 figure 22. soft-start at full load channel 2 figure 23. soft-discharge shutdown channel 1 figure 24. soft-discharge shutdown channel 2 figure 25. steady state operation at no load with frequency = 8mhz channel 1 figure 26. steady state operation at no load with frequency = 8mhz channel 2 typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 2.8v to 5.5v, en = v in , l 1 = l 2 = 1.2h, c 1 = 10f, c 2 = c 4 = 22f, i out1 = 0a to 2a, i out2 = 0a to 1.7a. (continued) en1 2v/div il1 1a/div v out1 1v/div pg 5v/div tb = 500s/div en2 2v/div il2 1a/div v out2 1v/div pg 5v/div tb = 500s/div en1 2v/div il1 0.2a/div v out1 1v/div pg 5v/div tb = 200s/div en2 2v/div il2 0.2a/div v out2 1v/div pg 5v/div tb = 200s/div sync 2v/div lx1 2v/div il1 0.2a/div v out1 ripple 20mv/div tb = 100ns/div sync 2v/div lx2 2v/div il2 0.2a/div v out2 ripple 20mv/div tb = 100ns/div
ISL78322 fn7908 rev 3.00 page 11 of 17 november 30, 2016 figure 27. steady state operation at full load with frequency = 8mhz channel 1 figure 28. steady state operation at full load with frequency = 8mhz channel 2 figure 29. v out1 hard short to v in negative current waveforms at high line channel 1 figure 30. recovery from ha rd short negative current waveforms v out1 channel 1 figure 31. v out2 hard short to v in negative current waveforms at high line channel 2 figure 32. recovery from ha rd short negative current waveforms v out2 channel 2 typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 2.8v to 5.5v, en = v in , l 1 = l 2 = 1.2h, c 1 = 10f, c 2 = c 4 = 22f, i out1 = 0a to 2a, i out2 = 0a to 1.7a. (continued) sync 2v/div lx1 2v/div il1 1a/div v out1 ripple 20mv/div tb = 100ns/div sync 2v/div lx2 2v/div il2 0.5a/div v out2 ripple 20mv/div tb = 100ns/div pg 1v/div il1 0.5a/div tb = 1s/div lx1 2v/div v out1 2v/div pg 1v/div lx1 2v/div il1 0.5a/div v out1 2v/div tb = 1s/div pg 1v/div lx2 2v/div il2 0.5a/div v out2 2v/div tb = 10s/div pg 1v/div lx2 2v/div il2 0.5a/div v out2 2v/div tb = 1s/div
ISL78322 fn7908 rev 3.00 page 12 of 17 november 30, 2016 figure 33. output short-circuit channel 1 figure 34. output short-circuit recovery channel 1 figure 35. output short-circuit channel 2 figure 36. output short-circuit recovery channel 2 typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 2.8v to 5.5v, en = v in , l 1 = l 2 = 1.2h, c 1 = 10f, c 2 = c 4 = 22f, i out1 = 0a to 2a, i out2 = 0a to 1.7a. (continued) lx1 5v/div il1 2a/div v out1 2v/div pg 5v/div tb = 5s/div lx1 5v/div il1 2a/div v out1 2v/div pg 5v/div tb = 1ms/div lx2 5v/div il2 2a/div v out2 1v/div pg 5v/div tb = 5s/div lx2 5v/div il2 2a/div v out2 1v/div pg 5v/div tb = 1ms/div
ISL78322 fn7908 rev 3.00 page 13 of 17 november 30, 2016 theory of operation the ISL78322 is a dual 2a/1.7a step-down switching regulator optimized for battery-powered or mobile applications. the regulator operates at 2.25mhz fixed switching frequency under heavy load condition to allow small external inductor and capacitors to be used for minimal printed circuit board (pcb) area. at light load, the regulator reduces the switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. the two channels are 180 out-of-phase operation. the supply current is typically only 6.5a when the regulator is shut down. pwm control scheme pulling the sync pin low (<0.4v) forces the converter into pwm mode in the next switching cycle regardless of output current. each of the channels of the ISL78322 employ the current-mode pulse-width modulation (pwm) control scheme for fast transient response and pulse-by-pulse cu rrent limiting shown in the ? block diagram ? on page 3 . the current loop consists of the oscillator, the pwm comparator comp, current sensing circuit, and the slope compensation for the current loop stability. the current sensing circuit consists of the resistance of the p-channel mosfet when it is turned on and the current sense amplifier csa1 (or csa2 on channel 2). the gain for the current sensing circuit is typically 0.32v/a. the control reference for the current loops comes from the error amplifier eamp of the voltage loop. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp up. when the sum of the current amplifier csa1 (or csa2) and the compensation slope (0.9v/s) reaches the control reference of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the p-mosfet and to turn on the n-channel mosfet. the n-mosfet stays on until the end of the pwm cycle. figure 37 shows the typical operating waveforms during the pwm operation. the dotted lines illustra te the sum of the compensation ramp and the current-sens e amplifier csa_ output. the output voltage is regulated by controlling the reference voltage to the current loop. the bandgap circuit outputs a 0.6v reference voltage to the voltage control loop. the feedback signal comes from the v fb pin. the soft-start block only affects the operation during the start-up and will be discussed separately shortly. the error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. the voltage loop is internally compensated with the 27pf and 250k rc network. the maximum eamp voltage output is precisely clamped to 1.8v. synchronization control the frequency of operation can be synchronized up to 8mhz by an external signal applied to the sync pin. the 1st falling edge on the sync triggered the rising edge of the pwm on pulse of channel 1. the 2nd falling edge of the sync triggers the rising edge of the pwm on pulse of the channel 2. this process alternates indefinitely allowing 180 output phase operation between the two channels. the internal frequency will take control when the divided external sync is lower than 2.25mhz. the falling edge on the sync trig gers the rising edge of the pwm on pulse. positive and negative overcurrent protection csa1 and csa2 are used to monitor output 1 and output 2 channels respectively. the overcurrent protection is realized by monitoring the csa_ output with the ocp threshold logic, as shown in the ? block diagram ? on page 3 . the current sensing circuit has a gain of 0.32v/a, from the p-mosfet current to the csa_ output. when the csa_ ou tput reaches the threshold of 1.25v for channel 1 and 1.1v for channel 2, the ocp comparator is tripped to turn off the p-mosfet immediately. the overcurrent function protects the switching converter from a shorted output by monitoring the current flowin g through the upper mosfets. upon detection of an overcurrent condition, the upper mosfet will be immediately turned off an d will not be turned on again until the next switching cycle. upon detection of the initial overcurrent condition, the overcurrent fault counter is set to 1 and the overcurrent condition flag is set from low to high. if, on the subsequent cycle, another overcurrent condition is detected, the oc fault counter will be incremented. if there are 17 sequential oc fault detections, the regulator will be shut down under an overcurrent fault condition. an overcurrent fault condition will result with the regu lator attempting to restart in a hiccup mode with the delay between restarts being four soft-start periods. at the end of the fourth soft-start wait period, the fault counters are reset and soft-start is attempted again. if the overcurrent condition goes away prior to the oc fault counter reaching a count of four, the ov ercurrent condition flag will set back to low. in the event that the inductor current reaches -1.6a, the part enters negative overcurrent protection. at this point, all switching stops and the part enters tri-state mode while the figure 37. pwm operation waveforms v eamp v csa duty cycle i l v out
ISL78322 fn7908 rev 3.00 page 14 of 17 november 30, 2016 pull-down fet is discharging the output until it reaches normal regulation voltage, then the ic restarts switching. pg the power-good signal (pg), monitors both of the output channels. when powering up, the open-collector power-on reset output holds low for about 1ms after v o1 and v o2 reaches the preset voltages. the pg output also serves as a 1ms delayed power-good signal. if one of the outputs is disabled, then pg only monitors the active channels. there is an internal 1m pull-up resistor. uvlo when the input voltage is below the undervoltage lockout (uvlo) threshold, the regulator is disabled. enable the enable (en1, en2) input allows the user to control the turning on or off of the regulator for purposes such as power-up sequencing. the regulator is enabled, there is typically a 600s delay for waking up the bandgap reference and the soft start-up begins. soft start-up the soft start-up eliminates the inrush current during start-up. the soft-start block outputs a ramp reference to both the voltage loop and the current loop. the two ramps limit the inductor current rising speed as well as th e output voltage speed so that the output voltage rises in a controlled fashion. at the very beginning of the start-up, the feedback voltage is less than 0.2v; hence the pwm operating frequency is 1/3 of the normal frequency. in forced pwm mode, the ic will start-up in pulse frequency mode to support prebiased load applications. during soft-start period, the devi ce will operate in tri-state mode, with both high-side and low-side drivers off to prevent negative inductor current flow in output stage. once soft-start is completed, the drivers will allow negative inductor current. by this time, the output should reach regulation. discharge mode (soft-stop) when a transition to shutdown mode occurs, or the output undervoltage fault latch is set, the outputs discharge to gnd through an internal 100 switch. power mosfets the power mosfets are optimized for best efficiency. the on-resistance for the p-mosfet is typically 100m and the on-resistance for the n-mosfet is typical 90m . 100% duty cycle the ISL78322 features 100% duty cycle operation to maximize the battery life. when the battery voltage drops to a level that the ISL78322 can no longer maintain the regulation at the output, the regulator completely turns on the p-mosfet. the maximum dropout voltage under the 100% duty-cycle operation is the product of the load current and the on-resistance of the p-mosfet. thermal shutdown the ISL78322 has built-in thermal protection. when the internal temperature reaches +150c, the regulator is completely shut down. as the temperature drops to +130c, the ISL78322 resumes operation by stepping through a soft start-up. applications information output inductor and capacitor selection to consider steady state and transient operation, ISL78322 typically uses a 1.2h output inductor. higher or lower inductor values can be used to optimize the total converter system performance. for example, for higher output voltage 3.3v applications, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. the inductor ripple current can be expressed as in equation 1 : the inductor?s saturation current rating needs to be at least larger than the peak current. th e ISL78322 protects the typical peak current 3.2a/2.8a. the saturation current needs to be over 3.6a for maximum output current application. ISL78322 uses internal compensa tion network and the output capacitor value is dependent on the output voltage. the ceramic capacitor is recommended to be x5r or x7r. the recommended minimum output capacitor values for the ISL78322 are shown in table 1 on page 2 . output voltage selection the output voltage of the regula tor can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. refer to ? t ypical applications ? on page 2 . the output voltage programming resistor, r 2 (or r 5 in channel 2), will depend on the desired output voltage of the regulator. the value for the feedback resistor is typically between 0 and 750k . let r 3 = 100k , then r 2 will be as shown in equation 2 : if the output voltage desired is 0.6v, then r 3 is left unpopulated and short r 2 . for better performance, add 10pf in parallel to r 2 . input capacitor selection the main functions for the in put capacitor is to provide decoupling of the parasitic induct ance and to provide a filtering function, which prevents the switching current from flowing back to the battery rail. one 10f x5r or x7r ceramic capacitor is a good starting point for the input capacitor selection per channel. an optional input inductor can be used before the ceramic capacitor to limit switching noise. it is recommended to limit the inductance less than 0.15h. ? i v o 1 v o v in --------- C ?? ?? ?? ? lf s ? -------------------------------------- - = (eq. 1) r 2 r 3 v out v fb --------------- - 1 C ?? ?? ?? = (eq. 2)
fn7908 rev 3.00 page 15 of 17 november 30, 2016 ISL78322 intersil automotive qualified products are manufactured, asse mbled and tested utilizing ts16949 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2012-2016. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. pcb layout recommendation the pcb layout is a very important converter design step to make sure the designed converter wo rks well. for ISL78322, the power loop is composed of the output in ductor l?s, the output capacitor c out1 and c out2 , the lx pins, and the gnd pin. it is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide. the switching node of the converter, the lx_ pins, and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. the input capacitor should be placed as close as possible to the vin pin and the ground of input and output capacitors should be connected as close as possible. the heat of the ic is mainly dissipated through the thermal pad. maximizing the copper area connected to the thermal pad is preferable. in addition, a solid ground plane is helpful for better emi performance. it is recommended to add at least five vias ground connection within the pad for the best thermal relief.
ISL78322 fn7908 rev 3.00 page 16 of 17 november 30, 2016 about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related docu mentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for in formational purposes only and is believ ed to be accurate, but not warranted. please visit our website to make sure you have the latest rev. date revision change november 30, 2016 fn7908.3 updated title updated features bullet 1 and added bullet 2. added related literature section. removed pfm information from document including text and figures. updated note 1. updated exposed pad pin description on page 4. removed quiescent supply current (top row only) from ec table removed peak skip limit from ec table removed sync logic input leakage current from ec table removed skip mode section. updated figures 1, 3, and 6 through 12. updated pod l12.4x3 to the latest revision. changes are as follows: -tiebar note 5 updated from: tiebar shown (if present) is a non-functional feature. to: tiebar shown (if present) is a non-functional feat ure and may be located on any of the 4 sides (or ends) august 26, 2014 fn7908.2 updated the ?esd rating? on page 5, ad ded the test method used for hbm and mm, changed cdm test method from ?jesd22-c101e? to ?aec-q100-11?. updated ?about intersil? on page 16 to new verbiage. january 14, 2014 fn7908.1 page 17 - 2nd line of the disclaimer changed from: "intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted" to: "intersil automotive qualified products are manufact ured, assembled and tested utilizing ts16949 quality systems as noted" - updated "products" verbiage to "about intersil" verbiage february 24, 2012 fn7908.0 initial release.
ISL78322 fn7908 rev 3.00 page 17 of 17 november 30, 2016 package outline drawing l12.4x3 12 lead dual flat no-lead plastic package rev 3, 3/15 1.70 +0.10/-0.15 12 x 0.40 0.10 12 0.10 12 x 0.23 +0.07/-0.05 4 7 ab c m pin #1 index area 6 1 2x 2.50 6 10x 0.50 3.30 +0.10/-0.15 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance: decimal 0.05 the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (4x) 0.15 3.00 index area 6 pin 1 4.00 b a 1.00 max see detail "x" c seating plane 0.08 c 0.10 c (3.30) 2.80 (10x 0.5) (12 x 0.23) (1.70) 12 x 0.60 0.2 ref c 0. 05 max. 0. 00 min. 5 compliant to jedec mo-229 v4030d-4 issue e. 7. 1 6 712 tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). for the most recent package outline drawing, see l12.4x3 .

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